Error masking in self-testable circuits

Abstract

The effects of error masking in a number of signature registers are analyzed. It is shown that a self-test can always be scheduled such that evaluating signatures only at the end of the complete test execution is sufficient. A method for computing the probability of a fault leading to at least one faulty signature in a set of self-test registers is presented. This method allows the computation of the fault coverage with respect to the complete test execution. A minimal subset of all self-test registers can be selected so that only the signatures of these self-test registers have to be evaluated and the fault coverage is almost not affected. The benefits of this approach are a smaller number of self-test registers in the scan path, a smaller number of signatures to be evaluated, a simplified test control unit, and hence a significant reduction in tie hardware required for built-in self-test structures. The proposed method is illustrated by an example and validated by simulation.