Universität Stuttgart
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Item Open Access 10 Gbit/s monolithic integrated Msm-photodiode AlGaAs/GaAs-HEMT optoelectronic receiver(1991) Hurm, Volker; Rosenzweig, Josef; Ludwig, Manfred; Benz, Willi; Osorio, Ricardo; Berroth, Manfred; Hülsmann, Axel; Kaufel, Gudrun; Köhler, Klaus; Raynor, Brian; Schneider, Joachim-Item Open Access 1.3 μm monolithic integrated optoelectronic receiver using InGaAs MSM photodiode and AlGaAs/GaAs HEMTs grown on GaAs(1994) Hurm, Volker; Benz, Willi; Berroth, Manfred; Fink, Thomas; Fritzsche, Daniel; Haupt, Michael; Hofmann, Peter; Köhler, Klaus; Ludwig, Manfred; Mause, Klaus; Raynor, Brian; Rosenzweig, JosefThe first 1.3 μm monolithic integrated optoelectronic receiver using an InGaAs MSM photodiode and AlGaAs/GaAs HEMTs grown on a GaAs substrate has been fabricated. At each differential output the transimpedance is 26.8 kΩ. The bandwidth of 430 MHz implies suitability for transmission rates up to 622 Mbit/s.Item Open Access Indirect optically controlled pseudomorphic HEMT based MMIC oscillator(1992) Bangert, Axel; Benz, Willi; Berroth, Manfred; Hülsmann, Axel; Hurm, Volker; Kaufel, Gudrun; Köhler, Klaus; Rosenzweig, Josef; Schneider, JoachimFor the first time an indirect optically controlled monolithic integrated oscillator was fabricated and examined experimentally. The oscillator was designed for a frequency of about 7 GHz. By illuminating a 60x60 μm2 photodiode by the light of a pigtailed laser diode (λ=840 nm), the free-running frequency of the oscillator was tunable in a range of more than 7 MHz. A locking range of more than 3 MHz was achieved. A phase shift in the output signal of nearly 180° has been observed.Item Open Access Digital dynamic frequency dividers for broad band application up to 60 GHz(1993) Thiede, Andreas; Berroth, Manfred; Tasker, Paul; Schlechtweg, Michael; Seibel, Jörg; Raynor, Brian; Hülsmann, Axel; Köhler, Klaus; Bronner, WolfgangA broadband dynamic frequency divider based on pseudomorphic Al0.2Ga0.8As/In0.25Ga0.75As MODFETs and passive loads is presented. Stable operation from 28 GHz up to 51 GHz with a power consumption of 440 mW could be shown. SPICE network simulation predicts operation in the 35 GHz - 60 GHz range for a divider circuit using an advanced E/D AlGaAs/InGaAs MODFET process.Item Open Access 10-20 Gbit/s GaAs/AlGaAs HEMT ICs for high speed data links(1992) Berroth, Manfred; Hurm, Volker; Lang, Manfred; Ludwig, Manfred; Nowotny, Ulrich; Wang, Zhigong; Wennekers, Peter; Hülsmann, Axel; Kaufel, Gudrun; Köhler, Klaus; Raynor, Brian; Schneider, JoachimA set of ICs has been developed for high-speed data links at data rates above 10 Gbit/s. A recessed gate process for double pulse doped quantum well transistors has been used with e-beam written 0.3- μm gates. A 4 bit multiplexer and a laser diode driver for the transmitter as well as a transimpedance amplifier, bit synchronizer, and 4 bit demultiplexer for the receiver have been successfully operated with data rates up to 20 Gbit/s.Item Open Access 20 Gb/s monolithic integrated clock recovery and data decision(1994) Wang, Zhigong; Berroth, Manfred; Hurm, Volker; Lang, Manfred; Hofmann, Peter; Hülsmann, Axel; Köhler, Klaus; Raynor, Brian; Schneider, JoachimAn IC for 20 Gb/s clock recovery and data decision was realised using 0.3 m gate-length QW-HEMTs. A narrow-band regenerative frequency divider with on-chip resonator filters is used for the clock recovery. The parallel processing concept is accepted for the data decision. The complex IC was tested on wafer using 5 and 10-Gb/s input data. The desired 10-GHz clock signal and regenerated data signals have been obtained. The 2x2 mm 2 IC has a power consumption of about 0.5 W at -3 volt supply voltage.Item Open Access 19 GHz monolithic integrated clock recovery using PLL and 0.3 μm gate-length quantum-well HEMTs(1994) Wang, Zhigong; Berroth, Manfred; Seibel, Jörg; Hofmann, Peter; Hülsmann, Axel; Köhler, Klaus; Raynor, Brian; Schneider, JoachimICs for optical data links have been developed for bit rates between 10 and 200 Gb/s. The only exception was the clock recovery (CR) IC at these high bit rates. In fact, the IC realization of CR is generally accepted as the weak point of high-speed system integration. While the bit rates of some ICs reach up to 40 Gb/s, monolithic ICs for a full CR function are limited to 2.5 Gb/s. The monolithic IC described here, for CR with a PLL including a full-balanced VCO, is based on the IC reported by Wang et. al. (1993). Clock frequencies up to 19 GHz are recovered with the IC reported here.Item Open Access 7.5 Gb/s monolithically integrated clock recovery using PLL and 0.3 μM gate length quantum well HEMTs(1993) Wang, Zhigong; Berroth, Manfred; Nowotny, Ulrich; Hofmann, Peter; Hülsmann, Axel; Köhler, Klaus; Raynor, Brian; Schneider, JoachimA monolithically integrated clock recovery (CR) circuit making use of the phase-locked loop (PLL) circuit technique and enhancement/depletion AlGaAs/GaAs quantum well high electron mobility transistors (QW-HEMTs) with gate lengths of 0.3 μm has been realized. A novel preprocessing circuit was used. In the PLL a fully-balanced varactorless VCO has been introduced. The VCO has a centre oscillating frequency of about 7.5 GHz and a tuning range greater than 500 MHz. A satisfactory clock signal has been obtained at the bit rate of about 7.5 Gb/s. The power consumption is less than 200 mW at the supply voltage of -5 V.