Please use this identifier to cite or link to this item: http://dx.doi.org/10.18419/opus-10316
Authors: Alavi, Golzar
Title: Hybrid system-in-foil integration and interconnection technology based on adaptive layout technique
Issue Date: 2019
metadata.ubs.publikation.typ: Dissertation
metadata.ubs.publikation.seiten: xix, 200
URI: http://elib.uni-stuttgart.de/handle/11682/10333
http://nbn-resolving.de/urn:nbn:de:bsz:93-opus-ds-103337
http://dx.doi.org/10.18419/opus-10316
metadata.ubs.bemerkung.extern: This work is funded by the German Research Foundation (DFG) the FFLexCom-Project under grant-no. BE 2256/25-1 and the German BMBF with the projects "KoSiF" (Project ID. 1612000461).
Abstract: The Hybrid System-in-Foil (HySiF) including ultra-thin embedded silicon chips in polymer foil in combination with large area electronics, such as organic thin-film transistors (OTFTs), capacitive sensors, antennas, and strain gauges is a promising technological solution for the next generation of consumers in the field of flexible electronics. This work mainly contributes to developing the CMOS-compatible process flow to embed and interconnect ultra-thin silicon chips inside polymer foil in combination with other devices. The fine-pitch (10 µm) chip to foil interconnectivity is pursued by relocating the active pads on a silicon chip to the foil periphery, therefore, saving silicon area and costs and providing a far larger I/O count is possible. The Chip-Film Patch (CFP) concept is suitable for HySiF technology. However, limitations often exist due to restriction in processing methods and incompatibility of the material with an IC processing fabrication line. These issues and corresponding solutions are treated in this thesis. Besides optimization of the already published concept of two-polymer CFP and bringing that to fabrication level, key aspects of this dissertation are: - The process flow development of face-up low-stress CFP technology to avoid the coefficient of thermal expansion (CTE) mismatch between embedded silicon chips, deposited polymer layers, and silicon substrate carrier. - The fabrication process of the face-down CFP technology to minimize topography on top of the embedded chip, thus, reaching finer pitch and pad size. Embedding devices with different thickness and chip backside processing are other advantages of the face-down CFP technology. - The challenge of unwanted rotation and positioning offset after chip embedding on foil using an adaptive layout technique based on laser direct writer lithography. Using the adaptive layout technique, wafer level embedding and interconnecting of multiple silicon chips as a HySiF become possible. The overlay accuracy below 1 µm in x-axis and y-axis for any arbitrary position of the embedded chip is achieved. - The thermal behavior of power chips embedding in polymer foil and self-heating phenomenon and corresponding cooling methods, such as heat spreader on the chip’s backside. - The CMOS-compatible process flow to fabricate a rigid mm-wave patch antenna and flexible dipole antenna in polymer foil with antennas that are fabricated, measured, and high-frequency properties of the polymer packages are extracted.
Appears in Collections:07 Fakultät Konstruktions-, Produktions- und Fahrzeugtechnik

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