Vertical Ge/SiGeSn-based p-channel nano field-effect transistors integrated on Si

Abstract

In this work, the fabrication and the electrical characterization of the germanium-based vertical p-channel planar-doped barrier field-effect transistor is investigated for the first time. Setting and adjusting the device design parameters and performing experimental iterations, the fabrication process was achieved successfully. Further enhancement of the device performance was accomplished through analysing the electrical characterization and introducing amendments to the fabrication process. Concurrently, a study of Ge/oxide interface was performed by introducing several surface treatments prior to gate oxide deposition and using capacitance voltage characterization to evaluate the resulting interface quality. The surface treatments were first applied to germanium-based metal-oxide-semiconductor capacitor structures that are integrated on silicon as well. Surface treatments included conventional and non-conventional treatment methods in addition to combinations of both. Subsequently, some of the best results were used in the transistor device fabrication to prove the validity of the results of this study. The results obtained for germanium-based planar-doped barrier field-effect transistor devices integrated on silicon are optimistic, using relatively large sized devices with a simple manufacturing process, which are competitive in electrostatic performance to more complicated and aggressively scaled devices from literature. Fabricated devices show the potential for energy efficient systems by achieving sufficiently low off currents. Furthermore, leakage current sources are studied through low temperature measurements and applying the studied surface treatment for additional possible progress. Low temperature measurements showed the potential of the superior device performance and competent subthreshold swing to literature, supported by simulation analysis of reduced effective oxide thickness. A comparison is demonstrated between this work and other similar channel length devices from literature that are defect free to elaborate the excellent possible performance of the devices in this work. Along with the fabrication and characterization of the devices, a simulation model based on extracted material data from the experimental work and literature is produced. Based on the model, a proposed design of a modified device using both planar doping and a heterostructure in the channel is then presented. The channel-engineered design uses a lattice-matched germanium/silicon-germanium-tin heterostructure within the channel that can be introduced at different positions. The results show improved performance by virtue of the larger energy band gap of the ternary alloy compared to germanium, leading to suppression of the leakage currents as well as a reduced subthreshold swing, making the heterostructure device promising for ultra-low power device applications.