Universität Stuttgart
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Item Open Access Active electronic loads for radiometric calibration(2017) Weissbrodt, Ernst; Kallfass, Ingmar (Prof. Dr.)Although radiometer systems are widely applied in very different fields, they all have one important requirement in common: They require a thorough radiometric calibration. Various conventional calibration references are well established, but their bulkiness, high power consumption, and complexity are limiting the expanding fields of application. Since novel industrial applications such as passive millimeter-wave imaging emerge, the requirements for calibration references have increased drastically. But also in scientific fields like radio astronomy, cosmology or environmental monitoring, modern remote sensing radiometers do not rely only on conventional references anymore. In this work, millimeter-wave monolithic integrated circuits (MMICs) based on metamorphic high electron mobility transistors (mHEMT) were designed to be used as active electronic loads for radiometric calibration. These novel references have not only the outstanding property, that they can be directly integrated on chip-level into the radiometer front-end, but also, that they can exhibit cold as well as hot reference noise temperatures. Since this is achieved without any physical cooling or heating, the power consumption is notably reduced. By monolithic integration of field effect transistor (FET) switches, theses multiple references can internally be routed to the receiver input without any mechanical wear. As a result, laborious external references can be omitted and the repetition rate of the calibration procedure increased, which results in a higher radiometric accuracy and allows a more compact and cost-effective design of modern radiometer systems. This work presents the first radiometric calibration front-end that allows to internally switch between active electronic cold and active electronic hot loads, as well as a passive ambient load. All components are integrated on a single MMIC, and a patent was granted for this innovation. To predict the achievable noise temperatures of active cold loads (ACLs), different simulation approaches were previously published. This work evaluates and adapts these existing approaches to design and manufacture several W-band loads. But the required design-flow was found to be very time-consuming because multiple iterations are necessary to successively design and optimize the input- and output matching networks, and to finally achieve the desired low noise temperature. Therefore, a novel simulation approach is introduced that makes efficiently use of modern optimization algorithms and the very accurate model library of the mHEMT technology and the passive structures. With this novel simulation method, the first active hot loads (AHLs) were designed as well as state-of-the-art ACLs up to 140 GHz. However, the characterization of low-noise one-port devices is particularly challenging, especially at such high frequencies. Hence, a substantial part of this work is to investigate the reliability of different noise measurement setups and the repeatability of noise temperature results. Dedicated setups in W- and D-band are used to characterize all manufactured active loads and some selected results are cross-checked by measuring the same circuits with independently designed measurement systems of other research facilities. The discrepant results are discussed, concluding that high variations in measured one-port noise temperature do not allow to rely on one single measurement setup. At the same time, this thorough investigation and comparison permits to establish an accuracy range within which the results of the manufactured active electronic loads are reliable, whereas other previously published ACLs are typically only measured with one measurement setup.Item Open Access Novel characterization techniques for the study of the dynamic behavior of silicon carbide power MOSFETs(2022) Salcines, Cristino; Kallfass, Ingmar (Prof. Dr.-Ing.)This dissertation provides insight into the dynamic behavior of SiC power MOSFETs from their inherent static IV and CV characteristics. While conventional dynamic measurements extracted from a DPT or a similar dynamic test-bench yield accurate quantitative data, the static IV and CV characteristics of a power semiconductor device offer more qualitative information to delve into the root mechanisms responsible for its dynamic behavior. Conventional characterization techniques are limited to power levels way below those which the power device withstands in the application. As a result, the static IV and CV characteristics attained by available measurement solutions are reduced to a limited scope of bias conditions insufficient to infer information about the dynamic behavior of the power device. This work tackles this gap and proposes novel measurement techniques that enable the characterization of the static IV and CV characteristics of SiC power MOSFETs at the full range of bias conditions the power device goes through in the application. Iso-thermal IV characteristics of a commercially available SiC power MOSFET are measured up to 40 kW power (instantaneous 50 A and 800 V) at junction temperatures ranging from 25°C to 175 °C. The CV characteristics are mapped at drain-source and gate-source bias combinations of VDS = 0 - 40 V and VGS = 0 - 20 V, respectively, at junction temperatures ranging from 25°C to 150 °C. The results of these measurements reveal unique insights into the electrical characteristics of SiC power MOSFETs which impact their performance in the application and explain unclear phenomena observed in their dynamic behavior. On the one hand, the intrinsic capacitances of the SiC power MOSFET extend their non-linearity, function of both VGS and VDS, to the saturation region of the power device. Moreover, they are also affected by the junction temperature of the power device. The impact of these in the voltage commutation speed of the device under different switching conditions is thoroughly analyzed in the thesis. On the other hand, the IV characteristics of the SiC power MOSFET reveal the existence of short channel effects that drastically affect the transconductance of the power device in its high voltage saturation region. Furthermore, the measurements show a positive temperature coefficient of the drain current in the high voltage saturation region of the SiC power device, attributed to the density of trap energy states in the SiC/SiO2 interface. These effects effectively lower the plateau voltage of the device and lead to faster current commutation speeds in the application than those expected from the datasheet values. The insights revealed by the proposed characterization techniques are intended to help fine-tune semiconductor technology processes and improve the accuracy of simulation models to achieve a higher grade of optimization in the design of future SiC-based energy conversion circuits.Item Open Access Design of frequency-converting monolithic integrated circuits for millimeter-wave applications(2022) Grötsch, Christopher; Kallfass, Ingmar (Prof. Dr.-Ing.)This thesis focuses on how to efficiently utilize the low terahertz spectrum in the frequency range from 220 to 325 GHz, also called H-band. This work presents an introduction on several techniques necessary for designing frequency-converting monolithic millimeter-wave integrated circuits for this frequency range. Six different frequency-converter MMICs in a 35 nm gate-length InGaAs mHEMT technology are presented: a nonlinear resistance up- and down-converter, a dual-gate up and down-converter, a gate-pumped transconductance up-converter and a half Gilbert cell up-converter. Each design is explained in detail, their advantages and their disadvantages are evaluated. Three examples will be given where a selection of the frequency-converter architectures are integrated with other functional stages like frequency multipliers and amplifiers to form a millimeter-wave transceiver: a highly linear FMCW radar receiver with a 50 GHz bandwidth, a heterodyne communication receiver facilitating multi-channel transmissions with carrier aggregation at W-band and a homodyne communication receiver with an integrated antenna for low-cost assembly on a PCB. Thereby, this thesis provides insight into the design considerations of terahertz frequency converters, the trade-off of different circuit architectures and topologies for certain applications, the obstacles that can occur during their development and approaches to overcome them.Item Open Access A comparison of system architectures for wireless links in the terahertz band(2022) Dan, Iulia; Kallfass, Ingmar (Prof. Dr.-Ing.)This thesis shows an in-depth analysis of two system architecures used for future terahertz communication systems. For each architecture wireless data transmissions are carried out based on analog frontend devices that use that particular architecuture. The performance of the links is compared and the structure of the wireless links is described in detail and analyzed.Item Open Access Multi-gigabit millimeter wave communication links(2015) Antes, Jochen; Kallfass, Ingmar (Prof. Dr.-Ing.)This dissertation is concerned with the search for new approaches to realize multi-gigabit wireless communication links. To satisfy the consumers’ growing demand for high-speed mobile connections, the achievable data rate in future wireless front- and backhaul applications, building the mobile network’s backbone, but also in short range wireless connections, needs to be significantly increased. Following latest discussions and statements, data rates well beyond 10 Gbit/s will be necessary for these use cases. To the present day, such wireless links are realized in the microwave regime, where the maximum data rates are limited by the restricted bandwidths achievable technologically at these carrier frequencies, as well as restraining frequency allocations. First approaches utilizing frequencies in the higher millimeter wave regime, i.e. above of 100 GHz, so far only operate with bandwidth-inefficient amplitude shift keying signals or use opto-electronics to generate a millimeter wave signal. The latter systems are also capable of using complex modulation formats but, up to now, are limited by comparably low transmit powers. To provide wireless links enabling multi-gigabit capacities combined with adequate reliability, new approaches in the realization of such systems will be necessary. The use of electrical millimeter wave integrated circuits, capable of operating in this high frequency regime, will result in compact, light-weight and easy-to-deploy frontend components and also allow to transmit over much higher distances. Combining the advantages of extremely high bandwidths achievable with these circuits with the possibility of using bandwidth efficient complex modulation formats will take wireless com- munication to a new level. The challenge hereby is to relate effects intro- duced on component level to repercussions which appear on system level, and, in a further step, reveal their impact and optimization potential. In this thesis, the necessary aspects for the realization of all-electrical multi-gigabit wireless communication system in the millimeter wave regime are considered. A study of appropriate approaches of circuit topologies suitable to realize extremely broadband transmit and receive components allowing for multi-gigabit capability, as well as the design and realization of such circuits build the basis for a profound analysis of such transmission systems. An investigation of the wireless system’s transmission quality under the influence of the frontend component’s non-idealities reveal the system’s limits but also the optimization poten- tial. Finally, free space data transmission experiments are conducted to prove the feasibility of multi-gigabit communication links operating at such elevated frequencies. In this dissertation, for the first time, system imperfections of millimeter wave communication links are related to the causative frontend non- ideality in a theoretical approach. The findings are verified by measure- ments. Furthermore, for the first time, outdoor transmission experiments across realistic distances unveiling the real potential of the proposed system solutions are shown.Item Open Access Switching characteristics of integrated GaN-on-Si half-bridge and driver circuits(2021) Mönch, Stefan; Kallfass, Ingmar (Prof. Dr.-Ing.)This work examines particularities in the switching characteristics of gallium nitride (GaN) half-bridge and driver circuits, which arise from the integration on a common conductive silicon (Si) substrate, or from the operation of discrete devices on an electrically coupled Si substrate. The supposed advantages of monolithic integrated half-bridges and drivers are promising: The reduced parasitic interconnect inductance improves voltage-switching transitions. The Si carrier allows low-cost and large-scale fabrication. A single integrated IC simplifies the assembly compared to conventional multi-chip power modules. However, the operation of such monolithic GaN-on-Si power circuits also evokes substrate-related effects, especially at elevated operation voltages, which were previously not relevant for single low-side GaN HEMTs. On the one hand, deteriorating effects such as on-resistance increase by negative substrate biasing (back-gating) have to be considered. On the other hand, beneficial effects such as the possibility of decoupling of substrate capacitances can be exploited for reduction of switching energies and consequently increased efficiencies compared to conventional discrete GaN power transistors. Furthermore, even though the monolithic integration of a gate driver with a power transistor reduces the interconnect parasitics between the driver and the transistor, still external interconnects to decoupling capacitors are required. The monolithic integration of half-bridges and drivers thus does not fully eliminate parasitic gate-loop and power-loop inductance. Therefore, advanced assembly technologies such as PCB-embedding of GaN-based power integrated circuits should also be considered in combination with the monolithic circuit integration. First, this work provides a theoretical framework to calculate and compare the effect of substrate-capacitances on application-oriented half-bridge capacitances for different feasible substrate terminations of discrete and monolithic GaN-on-Si half-bridges. It is explained and verified how floating substrate terminations reduce the effective output capacitances. To harness the benefits of this reduced effective capacitances, an improved passive substrate biasing network for monolithic half-bridges is proposed and experimentally verified: The proposed operation scheme for monolithic half-bridges avoids negative back-gating in all operation points of a dc-dc converter and at the same time has reduced effective output capacitance compared to a discrete half-bridge. Experimental operation of a monolithic half-bridge with the proposed substrate biasing network shows increased efficiency compared to a discrete half-bridge and verifies the effectiveness of the proposed duty-cycle independent floating substrate biasing. Compared to a conventional discrete half-bridge with two substrate-to-source terminated transistors, this work's operation scheme for a monolithic half-bridge in a dc-dc converter with 200 V input voltage, 100 V output voltage, 1.5 A load current and 100 kHz switching frequency, reduced the switching energies by over 20%, and the total power loss in a dc-dc converter by over 10%. This efficiency improvement is the results of this work's beneficial combination of a (semi-)floating substrate which reduces the effective output capacitance, and the novel substrate biasing network which avoids negative back-gating during conduction phases by shifting the average substrate voltage towards higher values. Then, this work work analyzes high slew-rate voltage switching transitions and the effect of parasitic inductance in the power-loop on switch-node overshoot voltage. An equivalent circuit analysis is carried out, which takes the limited voltage slew-rate of a power transistor into account. In contrast to a simplified RLC-circuit analysis with a infinitely fast voltage excitation pulse, this work analytically provides insight into the dependency of switch-node overshoot voltage on the voltage transition time. Even though the power-loop is almost undamped due to the low on-resistance of the transistors, the analysis shows that local minima of overshoot as a function of switching time exist, and by selection of optimal switching times it is possible to minimize the overshoot without a significant reduction of switching speed. Furthermore, an advanced PCB-embedded packaging technology is combined with on-package gate and dc-link capacitors, which further reduces parasitic inductance of GaN half-bridges with integrated drivers. Finally, this work exposes that the substrate-to-source termination of a lateral GaN power transistor, which is typically realized on the packaging level, forms a third parasitic loop. In addition to the well-known parasitic gate-loop and power-loop inductance, this work analyzes the effects of this substrate-loop inductance. An analytical and experimental stability analysis is carried out. Countermeasures are proposed to avoid instabilities from the parasitic-substrate loop. A substrate damping circuit is proposed, which avoids instabilities by damping of the substrate-loop, without slowing down of the switching transition. The experimental and theoretical investigation and results of this work on the switching characteristic of GaN-on-Si half-bridges with drivers on conductive Si substrates contributes to unlock the benefits of GaN HEMTs and monolithic power circuit integration for compact, clean switching and highly efficient power electronics.Item Open Access Entwicklung einer Methodik zur Bestimmung der Schaltverluste von diskreten 400V-GaN-Halbbrücken(2023) Bauer, Nikolas; Kallfass, Ingmar (Prof. Dr.-Ing.)Basierend auf aktuellen und zukünftigen Entwicklungsprämissen miniaturisierter automobiler Leistungselektronik wird in dieser Thesis die diskret verortete 400 Volt Gallium-Nitrid Halbbrücke als Kernkomponente einer fahrzeuggebundenen Hochvoltspeicher-Ladertopologie mit 3,7 Kilowatt Ladeleistung betrachtet. Die nachfolgende Methodikentwicklung zur Quantifizierung zeittransienten Schaltverhaltens und damit insbesondere generierter Halbbrückenverlustleistungen diskutiert die Vorteile der in dieser Arbeit entwickelten VERILOG Halbleitersimulation auf Basis verfügbarer ASM-HEMT Modelle der Compact Model Coalition gegenüber der Genauigkeit konventioneller SPICE-Simulation. Simulative Durchführungen dieser Arbeit berücksichtigen notwendige Betriebsparameter der Halbbrücke, insbesondere Totzeiten sowie deren Detektion per zum Patent angemeldeter Auswertelogik, und erlauben darüber hinaus in VERILOG die globale Schaltzellenoptimierung. Simulative Ergebnisse werden anhand einer dedizierten Power Factor Correction Stufe zeittransient und kalorimetrisch validiert. Die vorgestellten Simulationsmethodiken erlauben somit zukünftig die vollständig virtualisierte Hardwareauslegung von Leistungselektronik hinsichtlich Zeit- und Verlustverhalten.Item Open Access Efficient joint broadband radar and communication for airborne SAR imaging with small platforms(2024) Johannes, Winfried; Kallfass, Ingmar (Prof. Dr.-Ing.)Item Open Access Power semiconductor loss characterization and advanced thermal management for high power density AC/DC battery chargers(2024) Weimer, Julian; Kallfass, Ingmar (Prof. Dr.-Ing.)This dissertation investigates the challenges related to achieving higher power density in AC/DC battery chargers, particularly for compact electric vehicles such as e-bikes. The growing demand for battery-powered devices has driven the expansion of the global battery charger market, reaching a valuation of $24.5 billion in 2022. To support the transition to sustainable electrified transportation, it is essential to develop energy and resource-efficient designs, requiring power electronics capable of handling increased power density with enhanced efficiency and thermal management. Gallium nitride semiconductors have gained prominence in the battery charger domain due to their superior switching efficiency. This technology promotes the shift towards elevated switching frequencies, resulting in smaller passive components in power electronics. However, it also exposes significant electrical and thermal limitations that must be addressed to further enhance power density. Despite the minimal soft-switching loss energy of modern wide bandgap devices, substantial total losses emerge at multi-kilohertz operation. Furthermore, there is no standardized method for accurate characterization. Consequently, a consistent measurement approach is needed to optimize the multi-domain challenge within virtual prototyping based on precise loss models. Additionally, innovative thermal management concepts must be devised to tackle the constrained cooling capacity of increasingly smaller plastic housings, preventing power density limitations due to surface temperature standards. The research objectives of this work encompass the development of a rapid, non-invasive calorimetric characterization method for accurate soft-switching loss measurement, utilizing the results to design and construct a high-density mobile battery charger hardware prototype, proposing a novel thermal topology optimization concept for uniform charger surface temperature, and advancing thermal management to incorporate heat storage for achieving effective power density beyond the constraints imposed by continuous output power. The proposed concepts are validated through experiments and simulations, offering a comprehensive understanding of modern battery charger limitations and suggesting strategies to overcome them. This dissertation presents a high-density, two-stage battery charger prototype for compact electric vehicles, achieving a power density of 1.1 kW/dm³ with a system efficiency of 94.2 %, enabled by calorimetric semiconductor selection and loss modeling. Topology optimization employing accurate loss models can lead to a substantial improvement in system power density, up to 11.5 %, while limiting junction temperature increases. The proposed thermal management concept, utilizing heat storage, attained a 40 % higher power density for a 50 Wh battery by fully utilizing both static and dynamic cooling capabilities of the charger.Item Open Access Compact modeling of modern power MOSFETs based on industry-standard CMOS models(2025) Yan, Lixi; Kallfass, Ingmar (Prof. Dr.-Ing.)This work presents a modeling approach adopting the industry-standard models for circuit simulation with necessary extensions to describe vertical power MOSFETs. Standard models, which are developed for CMOS logic devices, are adopted with their proven robustness and fidelity to describe the voltage-controlled channel behavior of power MOSFETs. Considering the vertical MOSFET structure, the extended components including the nonlinear drift region, body-diode and the parasitic capacitance are defined as model extensions. The specific requirements for SiC MOSFETs different from the Si devices are also analyzed. The static and dynamic characteristics considering the thermal effects are measured as the reference for the model parameter extraction. Some attempts to create high voltage MOSFET models by adding elements to a standard MOSFET model are already reported, but these models are still not developed aiming at high current level power MOSFETs, or some crucial effects like the asymmetric reverse conducting current, reverse recovery of the body-diode etc. are not defined. This work provides a particular approach to characterize commercially available vertical power MOSFETs and proposes the modeling method describing the critical effects of power MOSFETs which enable the model to precisely describe the performance of the devices in switching mode simulations. Moreover, the model extension approach discussed in this work is not limited to a certain standard model. The physics based standard models can be categorized into three groups: threshold voltage based, inversion charge based, and surface potential based. The properties of three standard models from each group are analyzed and compared. The appropriate extension strategy is developed for each standard model and the specific parameter extraction flow is also provided for each proposed model. Compared with the vendor model, the modeling method proposed in this work can increase the accuracy of the simulation of the transient switching loss by around 20%, which can contribute to improve the power MOSFET compact modeling of the semiconductor community in view of improving the design of switched-mode power converters.